The development of microprocessor-based systems has resulted in the concurrent development of a variety of interconnect bus architectures for connecting microprocessors to other chips and devices within a system. Though initially such busses were implemented using parallel bus structures, serial bus structures have increasingly come into use to implement interconnect busses. This serialization of the interconnect busses has allowed existing networking technology to be used to create bus networks, sometimes referred to as “switch fabrics.” These switch fabrics may interconnect multiple microprocessors, peripheral chips, interfaces and other devices, while still retaining the underlying bus architecture. By retaining the underlying architecture, the use of switch fabrics becomes transparent to the connected devices, and such devices can thus be used with little or no modification.
Some switch fabrics incorporate bus architectures that are based on a hierarchical or inverted tree structure. In such a structure, busses may be fanned out starting with a single “root” bus, which is then coupled to one or more secondary busses through one or more switches. Each secondary bus can also in turn be coupled to additional busses through additional switches, continuing on in a chain that is limited only by the underlying bus architecture. But within such a hierarchical structure a device at the end of one branch may not be able to communicate with a device at the end of another branch without the communication passing through the root bus. Further, a device coupled to the root bus may not be able to access a device at the end of a branch if one of the intervening switches fails.